A conventional memory, for example, a DRAM, may include one transistor and one capacitor. However, there are limitations to the scalability of a conventional memory, due to the capacitor, in particular, the size of the capacitor. As a result, memories including one transistor (1T) and no capacitor as a memory cell, referred to as “capacitor-less” memories, have been developed. A capacitor-less memory cell may include a floating body (i.e., a body that is electrically floated).
Generally, a conventional capacitor-less memory cell utilizes a silicon-on-insulator (SOI) wafer and identifies data controlling the floating body voltage by accumulating a majority carrier (either holes or electrons) in a floating body or by emitting the majority carrier from the floating body. As understood by a person having ordinary skill in the art, a logic “1” may be written to and stored in a memory cell by causing the majority carriers to accumulate and be held in the floating body. As such, when the majority carrier is accumulated in the floating body, this state is generally referred to as a data “1” state. A logic “1” may be erased (i.e., logic “0” is written) by removing the majority carriers from the floating body. As such, when the majority carrier is evacuated from the floating body, this state is generally referred to as a data “0” state. As also understood by a person having ordinary skill in the art, the stored charge in the transistor floating body affects a threshold voltage (VT) of the memory cell transistor. A lower threshold voltage (VT) increases the current through the memory cell transistor, and a higher threshold voltage (VT) decreases the current though the transistor. The current through the memory cell transistor is used to determine the state of the memory cell.
FIG. 1 illustrates an example of a conventional floating body memory cell 10. Memory cell 10 includes a transistor 12 having a gate region 16, a source region 20, and a drain region 22. Source region 20 and drain region 22 are formed in silicon layer 26 with a floating body region 18 being defined therebetween. Moreover, floating body region 18 is disposed on a buried insulator 24 which overlies a substrate 28.
In operation, a logic “1” may be written to memory cell 10 by applying positive voltages to each of gate region 16 and drain region 22, wherein the positive voltage applied to drain region 22 is at a higher potential than the positive voltage applied to gate region 16. A lower positive gate potential and a higher positive drain potential produces, through impact ionization, holes (not shown) in floating body region 18. To write a logic “0”, gate region 16 may be coupled to a positive voltage and drain region 22 may be coupled to a negative voltage. The negative potential at drain region 22 causes an inverted channel and removes the holes from floating body region 18. Furthermore, to read a charge stored within memory cell 10, gate region 16 and drain region 22 are each coupled to positive voltages, wherein the positive voltage applied to drain region 22 is at a lower potential than the positive voltage applied to gate region 16. When holes are present in floating body region 18, a high drain current results in a logic “1” reading. When holes are not present in floating body region 18, a low drain current results in a logic “0” reading.
As illustrated above, a conventional floating body memory cell stores charges within a floating body that is adjacent to the drain and source regions and, therefore, the stored charges have a tendency to leak out of the floating body during operation. Additionally, conventional floating body memory cells suffer from poor data retention due to charge lost from the floating body upon charge recombination at a source region during hold, read and write operations. Furthermore, because conventional floating body memory cells may have a small floating body, which is not configured to hold a substantial charge, any charge lost may result in a fluctuating or weakened signal.
There is a need for methods, devices, and systems for enhancing the functionality of floating body memory cells. Specifically, there is a need for methods, devices, and systems for increasing data retention of a floating body memory cell while decreasing disturbance of adjacent memory cells during writing and reading operations.